Computers typically execute a series of tasks suitable to the intended application. Some computers are provided with interrupts that allow the normal processing stream to be interrupted and reprioritized to allow immediate processing of a real-time sensitive task. Such interrupt driven systems can be considered to represent a two level structure that provides both background and foreground processing capabilities for time insensitive and real-time sensitive tasks, respectively.
In some applications, time sensitive tasks (as versus real-time sensitive or time insensitive) are present. For example, in a mobile two-way radio having radio functions controlled via a microprocessor, time insensitive tasks such as responding to an operator input, are easily handled by a typical background executive. Similarly, real-time sensitive tasks such as signal encoding and decoding, serial bus data reception, and tone generation can be well accommodated through use of an interrupt driven foreground executive. Time sensitive tasks, however, such as bus command interpretation, channel scanning, audio routing, and synthesizer programming are not well accommodated by prior art two level structures. In the past, such time sensitive tasks have either been added as extensions to one or more of the real-time tasks, or have been accommodated through multiple polling areas in the background executive. Both of these methods have obvious inherent inefficiences. In the alternative, computer hardware can be designed to allow a middle level of processing activity to accommodate time sensitive tasks. Unfortunately, though the latter solution would work well, it represents significant cost and design time.
A need therefore exists for a method of allowing an ordinary microprocessor having one or more interrupts to accommodate real-time sensitive, time sensitive, and time insensitive tasks in an appropriate way.